Non-linear quantization of reference amplitude level time crossing intervals

ABSTRACT

Method and apparatus for digitally encoding and decoding an electrical waveform such as a speech signal. The method of digitally encoding includes the steps of determining the time interval between successive occurrences of predetermined amplitudes, producing a quantized digital output indicative of the length of each time interval, modifying the quantized digital signal by the transposition of selected quantized pulse lengths into predetermined quantized pulse lengths thus producing a nonlinear quantization of the digital output signal. The method of decoding comprises the steps of determining the length of each pulse of the digital signal, delaying the digital signal while adjusting the frequency response of a variable output circuit in dependence on the pulse length, and passing the signal through the now adjusted output circuit.

United States Patent Patterson [54] NON-LINEAR QUANTIZATION OF REFERENCEAMPLITUDE LEVEL TIME CROSSING INTERVALS [72] Inventor: Thomas Patterson,Wayside, Ocean Road, Hart Station, Hartlepools, England 221 Filed: May14, 1970 211 Appl. No.: 37,170

[30] Foreign Application Priority Data Licklider, The Intelligibility ofAm- 15] 3,684,829 1 Aug. 15, 1972 plitude-Dichotomized Time-QuantizedSpeech Waves, The Journal of The Acoustical Society of America, Vol. 22,No. 6, 1950. p. 820- 823.

Primary Examiner-Kathleen H. Claffy Assistant Examiner-Jon BradfordLeaheey Att0rneyNorris & Bateman ABSTRACT Method and apparatus fordigitally encoding and decoding an electrical waveform such as a speechsignal. The method of digitally encoding includes the steps ofdetermining the time interval between successive occurrences ofpredetermined amplitudes, producing a quantized digital outputindicative of the length of each time interval, modifying the quantizeddigital signal by the transposition of selected quantized pulse lengthsinto predetermined quantized pulse lengths thus producing a non-linearquantization of the digital output signal. The method of decodingcomprises the steps of determining the length of each pulse of thedigital signal, delaying the digital signal while adjusting thefrequency response of a variable output circuit in dependence on thepulse length, and

passing the signal through the now adjusted output circuit.

22 Claims, 3 Drawing Figures PHENTEDAUBIB m2 3.684329 SHEET 1 0F 3FIG.1.

.INVENTOR THOMAS PATTERSON NORRIS & BATEMAN PNENTEDMIGIS m2 3.684.829

SHEET 2 BF 3 I I I I L INVENTOR THOMAS PATTERSON By WRHA J dd- NORRIS &BATEMN The present invention relates to encoding and decoding methodsand circuits, and particularly, but not exclusively, to improved methodsand circuits for encoding and decoding electrical signals correspondingto speech waveforms to and from a digital form.

Previously known systems for encoding speech waveforms, in general,provide an output signal which is related to the instantaneous height ofthe speech waveform. For example, in the so-called pulse code modulationsystem a speech waveform is sampled at regular intervals and a digitaloutputsignal related to the instantaneous height of the waveform isproduced. This system suffers from the disadvantage that in order toproduce intelligible results the frequency at which the speech waveformis sampled needs to be considerably greater than the highest frequencyin the speech waveform. Thus a relatively broad bandwidth is requiredfor transmission.

A signal which represents a function corresponding to the intervals atwhich a speech waveform changes sign, or achieves predeterminedamplitudes, may contain substantially the whole of the informationcontent of the speech waveform.

According to the present invention a method of digitally encoding anelectrical signal representing a waveform such as a speech waveformcomprises the steps of determining the time intervals between successiveoccurences of predetermined amplitudes, and producing a quantizeddigital output indicative of the length of each said time interval.

A digital output signal produced in this manner comprises a series oftime periods defined between instants when the signal changes state. Theterm quantized digital output" will be understood to mean a signal whichcan be represented by an integral number of pulses of finite length. Forexample a two state digital signal comprises a rectangular waveform allthe crests of which are at one level and all the troughs of which are atanother. The information carried by the signal is determined by the timeperiods between each change of state. For convenience these time periodswill be referred to herein as the pulse length of the signal and thisterm will be understood to refer tothe length of a trough of arectangular wave as well as to the length of a crest. Similarly, amulti-state signal may have, for example, a plurality of discreteamplitude states the pulse length of such a signal being the time periodfor which the signal remains in any one state.

The amplitudes which are used to detennine the time intervals betweensuccessive occurences thereof may be equal and of constant value, suchas zero, or may vary in dependence on the amplitude of the waveform tobe encoded or the frequency of the waveform to be encoded. A speechwaveform for example, normally varies in amplitude according as thefrequency varies so that the higher frequency components of the waveformare of substantially smaller amplitude than the lower frequencycomponents. lf a constant amplitude level is used to determine the saidintervals the input waveform may be suitably shaped by selectiveamplification of the low amplitude components to ensure that they allachieve the said amplitude. The

waveform may, for example, be reduced to asquare wave by infiniteclipping which may be achieved by passing the signal through a high gainamplifier operated under overload conditions.

The digital output may be regarded as a train of quanta where a quantumis represented by the longest pulse which can be used in integral numberto represent the waveform. Conveniently the pulse length is made at mostthe length of the shortest pulse of the electrical waveform to bequantized. The square waveform may be linearly quantized by passing theelectrical waveform through a coincidence circuit which is also fed withthe quantizing pulses in such a way that output pulses are'producedwhich are of the same length as the quantizing pulses. A trainof l "and0" pulses will then represent the input waveform which is howeveradjusted so that the pulse length of the'signal is an integral number ofquantizing pulses.

It will be apparent that the number (n) of quantizing pulses whichrepresents any given pulse length of the waveform will depend on therate of the quantizing pulses (Q) and the frequency (f) of the componentof the waveform which the pulse represents in the relation:

Thus the lowest rate of quantizing pulses will be Q 2f so that thehighest frequency will have a pulse length of l quantizing pulse. It canalso be shown that the next longer pulse length will represent afrequency of half the highest frequency, and similarly that each longerpulse will represent a frequency which is a larger fraction of thefrequency represented by the preceding pulse. For example, whereas thesecond shortest pulse represents a frequency of half that represented bythe shortest pulse, the fifteenth shortest pulse represents a frequencyof a fifteenth of that represented by the shortest pulse. in other wordsthe lower frequency components of the waveform are quantized more finelyand the higher frequency components are quantized more coarsely.

The higher frequency components of speech waveforms are, in general,more important than the lower frequency and so, in order to get thesecomponents quantized more finely the waveform may be frequency invertedbefore being passed to the infinite clipping circuit. This may be done,for example, by double side band modulating the signal waveform andfiltering out the upper side band to leave just the lower side bandwhich will be frequency inverted with respect to the signal waveform.

Alternatively, or in addition, the waveform may be quantized in anon-linear manner.

Preferably the quantized signal is modified by the transposition ofselected quantized pulse lengths into predetermined quantized pulselengths. Preferably the transposition is effected in such a way as toproduce a substantially equal number of different pulse lengths torepresent each octave within the frequency range of the original signalwaveform.

According to another aspect of the invention there is provided a circuitfor digitally encoding an electrical signal representing a waveform suchas a speech waveform comprising means for determining the time intervalsbetween successive occurences of predetermined amplitudes, and means forproducing a'quantized digital output signal indicative of the length ofeach said time interval.

Preferably there is provided an infinite clipping circuit fortransforming the signal waveform into a rectangular waveform.

The quantized digital signal is especially suitable for processing usingdigital techniques such as grouping, digital addition, subtraction ormultiplication to provide a coded signal of narrower bandwidth. Also thedigital signal could be used with a computer programmed to recognizesequences of digits to provide, say, a typewritten output from a spokeninput.

The digital signal may be decoded by filtering through a low pass filterwhich rounds the signal but this process is noisy and produces harmonicdistortions which reduce the quality of the signal. 1

According to another aspect of the present invention a circuit fordecoding a quantized digital signal of the type encoded in dependence onthe time intervals between successive occurences of predeterminedamplitudes in the original information signal, comprising means fordetermining the length of each successive pulse of the signal, means fordelaying the digital signal while a variable output circuit is adjusted,in dependence on the said pulse length, and then passing the digitalsignal to the output circuit, to provide an output waveform related tothe digital signal.

Preferably the output circuit is a variable low-pass filter circuit thefrequency response of which is adjusted such that the cut-off frequencyis decreased to a relatively low value for a long pulse and increased toa relatively high value for a short pulse.

Thus the frequency response of an output circuit is adjusted independence on the pulse length of the signal such that harmonicdistortion of the signal by the output circuit is reduced.

Conveniently the filter circuit is an n-pole Bessle filter.

Alternatively the variablejfilter circuit may comprise a plurality offixed filter circuits each having a different frequency response and acooperating switching circuit for selecting the appropriate filtercircuit in accordance with the length of the pulse to be decoded.

The present invention also provides a method of decoding a digitalsignal of the type encoded in dependence on the time intervals betweensuccessive occurences, in the original information signal, ofpredetermined amplitudes comprising the steps of determining the pulselength of the signal, delaying the signal while the frequency responseof a variable output circuit is adjusted in dependence on the pulselength and then passing the signal through the output circuit to providean output waveform corresponding to the digital signal.

Various embodiments of the invention will now be described, by way ofexample, with reference to the accompanying drawings, in which:

FIG. 1 is a schematic diagram of one embodiment of an encoding circuit;

FIG. 2 is a schematic diagram of one embodiment of a decoding circuit,and

FIG. 3 is a schematic diagram of an alternative embodiment of a decodingcircuit.

FIG. 1 shows one embodiment of a non-linear encoder. A linear encodercould comprise, in its simplest fonn, merely one'bistable circuit or anAND gate fed with clock pulses and the signal waveform to be encoded.The output from such a circuit would be a series of l pulsescorresponding to the peaks of the signal waveform and a 0" outputcorresponding to the troughs of the signal waveform. Clearly the higherthe clock rate the more nearly the envelope of the output waveform willresemble the input waveform.

Referring now to FIG. 1 there is shown a circuit for encoding an inputwaveform in a non-linear manner. The circuit is shown simplified for thesake of clarity by the omission of a number of stages of each shiftregister. In FIG. 1 the shift registers are shown having 10 stagesalthough it will be realized that the maximum number of stages used inany shift register in the encoder will be dependent on the lowestfrequency, that is the longest pulse, it is wished to transmit.

The input signal is fed into the serial input of a dual shift register600 comprising ten bistable circuits 601 to 610 and ten associated dualbistable circuits 611 to 620 the dual bistable circuits 61 1 to 620 areinterconnected with bistable circuits 601 to 610 such that associatedwith each bistable circuit 601 to 610 is a dual bistable circuit whichis always in the opposite state. The serial input of the shift registeris also fed with clock pulses at a predetermined rate from a clock 621.The serial output from shift register 600 is fed to a bistable circuit622 which has a dual circuit 623. The parallel output of each bistablecircuit 601 to 610 is fed to one input of a respective AND gate in abank of AND gates 624 to 633. Similarly the parallel outputs of the dualcircuits of the shift register are coupled each to a respective input ofAND gates 634 to 643. The other input of each AND gate is coupled to theoutput of its neighboring AND gate down the chain from 624, the secondinput of which is coupled to the output of AND gate 625, as far as 632.The second input of AND gate 633 is coupled via a controlled gate 644 tothe parallel output of bistable circuit 610. The AND gates 634 to 643are similarly interconnected, the second input of AND gate 643 beingcoupled to the parallel output of dual circuit 620, the last dual stageof shift register 600, via a controlled gate 645.

The control input of the controlled gate 644 is fed from a delay circuit646 via an inverting circuit 647 from the output of an OR gate 648. Theinputs to the OR gate 648 are coupled to the outputs of two AND gates649 and 650. One input of both AND gates 649 and 650 is connected to theparallel output of the last stage 610 of the shift register 600, theother input of AND gate 649 is coupled to the output of bistable circuit622 and the other input of AND gate 650 is coupled to the output of dualcircuit 623. Thus if the last stage 610 of the shift register is in a 0state neither AND gate 649 nor AND gate 650 will produce an output; thusOR gate 648 produces no output and the invetting circuit 647 produces al output so that controlled gate 644 is open.

A similar arrangement of components 651 to 655 controls gate 645 fromthe parallel output of the last dual stage 620 of the shift register 600and the output of the two bistable circuits 622 and 623. However, sincecircuit 610 is in a 0 state its dual circuit must be in a 1" state andsimilarly one or other of the circuits 622 and 623 must be in a I statesince one is the dual of the other, thus there will be an output fromone or other of the AND gates 654, 655 and OR gate 653 will consequentlyproduce a 1 signal which is converted to a by the inverting circuit 652and passed via delay circuit 651 to the control input of gate 645. Thuscontrol gate 645 is shut. It will be appreciated that gates 644 and 645are open and closed alternatively, that is if one is open the other isalways shut.

Consider, for example, an input signal comprising a train ofapproximately four I clock pulses in length followed by a train ofapproximately four 0 clock pulses in length entering the serial input ofthe shift register 600. Since the register operates only when asynchronizing clock pulse is received the input signal will be acceptedby the shift register as trains of exactly four clock pulses in length.The signal is passed down the shift register and has no effect until itreaches the last stage 610 of the shift register 600. Since the firstelement of the signal is a l pulse the last stage 610 of the shiftregister 600 must previously have been in a 0 state and thus, forreasons discussed above the gate 644 is open. The parallel output ofcircuit 610 passes to both inputs of AND gate 633 which thereforeswitches to a 1 state. The 1 output of AND gate 633 is passed to oneinput of AND gate 632 which, since its other input is coupled to theparallel output of circuit 609 which is in a l state, switches to a lstate and passes its output to AND gate 631. This process continuesuntil a 1 pulse is received by AND gate 629 from AND gate 630 which,since the second input is connected to the parallel output of circuit606 which is in a 0 state, does not switch on.

The switching time of the AND gates is very much shorter than the clockpulse intervals and so this switching will be accomplished substantiallyinstantaneously. As discussed above once the circuit 610 switches to a lstate the gate 644 switches off after a delay determined by the delaycircuit 646. This delay, although only a fraction of a clock pulse willstill be substantially longer than the time taken for the AND gates 630to 633 in the chain to switch on so that when the gate 644 closes theAND gates will have switched, as described, but will not again beaffectedby the parallel outputs of the shift register untilthe gate 644is opened when the last stage 610 of the shift register 600 nextswitches to a 0 state.

The outputs of the AND gates are also coupled to the parallel inputs ofa shift register 656 comprising, in this case, 10 bistable circuits 657to 666. The connections between the AND gates 624 to 633 and thebistable circuits 657 to 666 are made in accordance with the nonlinearquantization encoding pattern to be used. In this case the encodingpattern IS! IN OUT Thus although the input signal may vary by integersbetween 1 and 10 the output of the encoder will only be pulses of one offour lengths, that is the output signal pulses will be either 2, 3, 6 or8 clock pulses long.

In order to achieve this pattern the outputs of AND gates 633 and 632are both connected to the inputs of bistable circuits 665 and 666 sothat if only AND gate 633 is switched on its output will switch bothcircuits 665 and 666 to a 1" state. Similarly the outputs of both ANDgates 630 and 631 are connected to bistable circuit 664 so that whetherone or both of them is/are switched on the circuit 664 will be switchedto a l state. The serial output of shift register 656 is fed out at theclock rate, (the serial input being fed from the clock 621) so that, inthe example under discussion the four l pulses on shift register 600will switch on the four AND gates 630 to 633 which in turn will switchthe three bistable circuits 664 to 666 to a 1" state.

These will be pulsed out of the serial output of shift rev gister 656 toan adding circuit 667 where the voltage level is adjusted so that 1 and0 signals are spaced equally on either side of a datum value, normallyzero.

Meanwhile, before the first clock pulse occurs to start feeding out the1" signals from the shift register 656, the parallel outputs from thebistable circuits 664 to 666 are fed back to the preset inputs ofbistable circuits 608 to 610 to preset the state of these circuits to 1"to conform with the state of the last three stages of shift register656. in the present case these circuits are already in a 1 state and sono change is made but if it had merely been a single 1 pulse on circuit610 this would have caused both circuits 665 and 666 to switch to a lstate and thus when these parallel outputs are fed back the circuit 609would be switched from a 0 to a 1" state. it is necessary for the lstates of the end stages of both shift registers to be the same so thatcontrolled gate 668 which controls the serial input of shift register656 is not prematurely closed.

Similarly to ensure that gate 668 is closed at the right time the inputsof an AND gate 669 are coupled to the parallel outputs of circuits 663and 664 as well. The input from circuit 663 is inverted so that a lsignal is produced by AND gate 669 whenever circuit 664 is in a l statewhile circuit 663 is in a 0 state. The output of this AND gate iscoupled to the preset input of dual circuit 617 to preset this to a lstate when a l pulse is produced. The circuit 607 is thus switched to a0 state so that the last stage of shift register 600 will switch to a 0state at the same time as the last stage of shift register 656.

This means that the four l pulses followed by four 0 pulses in shiftregister 600 have been converted to three l pulses followed by five 0pulses. Thus after three clock pulses the last stage of shift register600 will switch to a 0 state. This via OR gate 648 will switch off gate668.

Dual circuit 620 will now switch to a l state. While the 1 signals werepassing out of shift register 600 the last dual stage 620 of theregister was in a 0 state and thus the gate 645 is open. The five ANDgates 639 to 643 will be switched on as described in relation to thebank of AND gates 624 to 623. A controlled gate 681 which controls theserial input clock pulses to a shift register 670 is opened, and, aftera delay determined by delay circuit 651, the gate 645 is closed.

The outputs of AND gates 634 to 643 are coupled to the parallel inputsof bistable circuits 671 to 680 forming shift register 670 in a manneridentical to that of the connections between AND gates .624 to 633 andshift register 656 to produce the quantizing pattern shown above. Theoutputs from the five AND gates 639 to 643 switch the six bistablecircuits 675 to 680 to a l" state and the six l pulses are passed out ofthe shift register, they are converted to six pulses by an inverter 682and passed to adding circuit 667.

As before the parallel outputs of the bistable circuits 671 to 680 arefed back to the preset inputs of the bistable circuits v611 to 620 toensure that there are six l pulses within the dual side of shiftregister 600 to correspond to the six 1 pulses. Similarly an AND gate683, having its inputs connected to the parallel outputs of circuits 674and 675, the input from 674 being inverted, provides an output fed backto the preset input of bistable circuit 604 so that dual circuit 613will be converted to a 0" state if seven l pulses are on shift register600 since they would be transferred to form six l pulses on shiftregister 670.

lf the four 0 pulses of the initial signal are followed by a furtherfour l pulses these will have been shortened to three (when circuit 675fed back a l pulse to dual circuit 615 to adjust the train of five 1"pulses in the dual side of shift register 600 to correspond with the six1 pulses in shift register 670) and thus will pass, unadjusted, throughto shift register 656 as three I pulses. A following four 0 pulses willbe transmitted as three 0" pulses and as described above, a furtherfollowing four l pulses will be transmitted as six l pulses. Acontinuous train of four l pulses and four 0 pulses will give rise to atransmitted series of three 1 pulses, six 0 pulses, three l" pulses,three 0 pulses, six l pulses, three 0 pulses, three l pulses, six 0"pulses, and so on.

The output of the adding circuit 667 which is alternately fed with lpulses from shift register 656 and 0" pulses from shift register 670 ispassed via a control gate 684 to an output line 685.

The gate 684 operates to cut off the output line 685 in the intervalsbetween information signals such as the gaps between words in a speechwaveform. In such cases the shift register 600 fills up" with likepulses and this could lead to the generation of spurious signals. Toprevent this the input lines of an OR gate 686 are coupled to theoutputs of AND gates 624 and 634 so that if either side of shiftregister 600 fills up" with l pulses the OR gate will switch. The outputof OR gate 686 is coupled to the parallel input of a shift register 687.The serial input of shift register 687 is fed with clock pulses and theserial output is fed via an inverter 688 to the control input of gate684. Thus if OR gate produces a l output the whole of shift register 687fills with l pulses which, after passing through inverter 688, switchoff gate 684 and keep it off until the shift register 687 has clearedwhich, in this case, will be l0 clock pulses after the last l pulse fromOR gate 686.

' Referring now to FIG. 2 there is shown a schematic diagram of oneembodiment of a decoding circuit. The input stage of the decodingcircuit comprises a synchronous dual shift register generally indicated111. The synchronization of the shift register is controlled by a clock112. The dual shift register comprises on one side a plurality ofbistable elements 120 to 129 and on the dual side a plurality ofbistable elements indicated 130 to 139. It will be understood thatalthough only 10 bistable elements have been shown in the drawing thereare considerably more than this, the total number required beingdetermined by the longest pulse, representing the lowest frequency, tobe decoded.

The one side of the shift register 111, that is the side comprisingbistable elements 120 to 129, is fed with the signal to be decoded, andthe dual side of the shift re gister 111, that is the side comprisingthe bistable elements 130 to 139 is fed with the inverse signal. Thuswhen the one side is fed a l the dual side is fed a 0 and vice versa.

Each bistable element 120 to 129 in the one side of the shift register111 has a parallel output line to one input of an AND gate 140 to 149respectively and each bistable element 130 to 139 in the dual side ofthe shift register 111 has a parallel output line to one input of an ANDgate 150 to 159 respectively. The other input of each AND gate isconnected to the output of the next succeeding AND gate in the chainapart from AND gates 149 and 159 each of which have both inputsconnected together so that when the parallel output of bistable 129 or139 transmits a l output the AND gates 149 and 159 respectively transmita l output. Thus, for example, the output of AND gate 144 is coupled toone input of AND gate 143 the other input of which is coupled to theparallel output of bistable element 123.

The output of each AND gate is also coupled to one input of a respectivebistable circuit, AND gates 140 to 149 being coupled to bistablecircuits 160 to 169 respectively and AND gates 150 to 159 being coupledto bistable circuits 170 to 179 respectively. The groups of bistablecircuits 160 to 169 and 170 to 179 each have a clear input 113 and 114respectively which sets each circuit to give a 0 output. The bistable,circuits 160 to 169, and 170 to 179 are of the type which give a loutputafter a 1 from the input line and then continue to give a 1 outputregardless of the state of the input line until a 1 input is received onthe clear line. The circuit then produces a 0 output until the next 1signal from the input line.

The clear" line 113 is fed from the output of an AND gate 115 the inputsfrom which are fed from the output of the dual bistable circuit 139 andthe output of a bistable circuit 116 the input to which is fed from theoutput of bistable circuit 129. Since the dual bistable circuit 139 isalways in the opposite state to that of bistable circuit 129 the ANDgate will only produce an output when the output from bistable circuit116 is opposite to that of bistable 129, that is at the end of a trainof like pulses.

For example, assuming a train of 0" signals has just passed there willbe a 0 output state from bistable circuit 1 16 and a l output state frombistable circuits 126, 127, 128 and 129; bistable circuit will have a 0"output state. As the bistable circuit 129 changes from its 0 state toits l" state, passing the 0 signal to bistable circuit 116, the AND gate149, both inputs of which are fed from the parallel output of bistablecircuit 129, will produce a l output signal. This is passed to bistablecircuit 169 to produce a l state of that circuit and also to one inputof AND Gate 148. Since bistable circuit 128 is in a 1 state AND gate 148produces a l output which switches bistable circuit 168 to a 1" stateand passes to one input of AND gate 147. This process is repeatedsetting bistable circuits 167 and 166 to their l states. When the 1output of AND gate 146 is passed to the input of AND gate 145 theprocess stops because bistable circuit 125 is in a state and thus nooutput is produced by AND gate 145. Thus only bistable circuits 166 to169 are set into a l state even though one or more of the bistablecircuits 120 to 124 in the shift register may be in a 1 state it is nottransmitted via its appropriate AND gate as the chain is broken by thefirst 0 state. Since the switching time of the AND gates is in theregion of microseconds and the clock pulse rate is in the region ofmilliseconds the time taken to set the bistable circuits 166 to 169 totheir l states is negligible.

The l outputs of the bistable circuits are all passed to an addingcircuit 117 which produces a voltage signal proportional to the numberof circuits in the l state. The output of the adding circuit is passedto a reciprocal circuit 118 which gives an output voltage inverselyproportional to the sum of the number of circuits in the 1 state andthus inversely proportional to the number of pulses in the train andapproximately proportional to the frequency which this pulse trainrepresents. The output of the reciprocal circuit is passed via a gate 119 to the control input 180 of a variable filter 181 the pass band ofwhich is variable in dependence on the voltage applied to the controlinput 180. That is a relatively high voltage at the control input 180produces a relatively wide pass band of the filter and a relatively lowvoltage at the control input 180 produces a relatively narrow pass bandof the filter.

As mentioned above the switching time for the AND gates and bistablecircuits is very much less than the clock pulse intervals and so thepass band of the variable filter is adjusted effectively as soon as thebistable circuit changes to a l state. The output of the bistablecircuit is connected via an adjusting circuit 182 and a controlled gate183 to the input of the variable filter 181. The purpose of theadjusting circuit 182 is to make the 0 and the l signals equally spacedabout a datum voltage, normally zero, as most bistable circuits producean output which is not equi-polar. The purpose of the gate 183 will bedescribed later.

The bistable circuit 116 has a dual bistable circuit 184 which is fedfrom the output of bistable circuit 139 which is the dual circuit ofbistable circuit 129. When the first of a train of 0" pulses arrives atcircuit 129 there will be a l pulse in circuit 116 a 0 pulse in circuit184 and a 1 pulse in circuit 139. The AND gate 115 thus produces a loutput which is trans mitted along the clear line 113 to set all thebistable circuits 160 to 169 to their 0 state. The inputs to AND gate149 from bistable circuit 129 are two 0 pulses, thus AND gate 149produces a 0" output and consequently all the AND gates 140 to 148 aresimilarly set to a 0 state in which they will all remain until a l pulsenext reaches bistable circuit 116.

The AND gate 159 however has both its inputs connected to the output ofdual bistable circuit 139 thus a 1" output from AND gate 159 is producedwhen a 0" pulse is received by bistable circuit 129. The AND gates 150to 159 are coupled together and to bistable circuits 170 to 179 in themanner described in relation to AND gates to 149 and bistable circuitsto 169 so that a train of l pulses on dual bistable circuits 130 to 139with one end at bistable circuit 139 will cause the corresponding ANDgates in the chain 150 to 159 to produce a 1 output and set thecorresponding bistable circuits in the chain to 179 to a 1 state. Thus achain of 0" pulses on the shift register with one end at bistable 129will cause a corresponding number of shift registers in the chain toswitch to a 1 state and produce a 1 output to be added in an analogueadding circuit 185. The adding circuit produces an output voltageproportional to the number of bistable circuits in the chain 170 to 179which are in the .1" state. The output from the analogue adder passesthrough a reciprocal circuit 186 which is identical with reciprocalcircuit 118, a gate 187, the purpose of which will be described later,to the control input 180 of the variable filter 181. Thus the variablefilter is set in accordance with the number of O pulses in the train ina like manner to that described for the train of l pulses.

The state of the bistable circuits 170 to 179 remains the same while thetrain of 0 pulses is passed through the filter until a l pulse isreceived at the bistable circuit 129. The dual bistable circuit 139 isthen in a 0" state. Circuit 116 is then in a 0 state (the last 0 of thetrain) and dual bistable circuit 184 is in a l state. The two inputs ofan AND gate 188 the output of which is coupled to the clear line 114 ofthe group of bistable circuits 170 to 179 are connected respectively tothe outputs of bistable circuit 129 and bistable circuit 184. Thus whenthe state of bistable 129 becomes dif ferent from that of bistablecircuit 116 a l output is produced by the AND gate 188 to clear all thebistable circuits in the group 170 to 179.

Thus the pass band of the filter 181 is adjusted by a signal from theshift register comprising bistable circuits 120 to 129 via the AND gates140 to 149 and the bistable circuits 160 to 169 for a series of l pulsesin the digital signal and the pass band of the filter 181 is adjusted bya signal from the dual shift register comprising bistable circuits 130to 139 via AND gates 150 to 159 and bistable circuits 170 to 179 for aseries of 0 pulses in the digital signal. Since the signal comprisesalternate trains of l and 0 pulses the groups of circuits associatedwithone side of the shift register-111 and the groups of circuitsassociated with the dual side of the shift register 111 operatealternately to control the filter 181.

During periods when the dual side is in operation, that is when a trainof O pulses is being passed through the filter 181, the group of ANDgates 140 to 149 produce no output signal and the group of bistablecircuits 160 to 169 are all in a 0 state. The analogue adding circuit117 thus produces no output and as a consequence the reciprocal circuit118 produces its highest output, this output is unwanted and wouldproduce a spurious adjustment of the filter 183 if it were to be passedto the filter control gate 180. This is prevented however by the gate 119 which is controlled by the output of an OR gate 189. The gate 119 isopen when a 1 pulse is applied to the control input whereupon the outputis the same as the input: when a 0" pulse is applied to the gate 190however the output is held at 0. Each of the two inputs to the OR gate189 is fed by the output of an AND gate 191 and 192 respectively. Theinputs to AND gate 191 are taken from the output of bistable circuit 129and dual bista-' ble circuit 184, and the inputs to AND gate 192 aretaken from the outputs of bistable circuit 129 and bistable circuit 116.Thus providing there is a 1 pulse at bistable circuit 129 forming thelast stage of the shift register 111 and either bistable circuit 116 orits dual circuit 184 is in a I state the gate 119 will be open. Nowsince at all times one or other of the dual circuit 184 and bistablecircuit 116 is in a I state the gate 119 will be open whenever there isa 1" pulse at the last stage 129 of the shift register 111. Conversely,since the inputs of both AND gates 191 and 192 are tied to the output ofbistable circuit 129 the gate 119 will always be closed whenever a pulsereaches the last stage 129 of the shift register 11 1.

Similarly the output of an OR gate 193 is connected to a control gate194 of the controlled gate 187. The inputs to the OR gate 193 areconnected to the outputs from two AND gates 194 and 195 the inputs ofwhich are both coupled to the output of the last dual stage 139 of theshift register 111 and respectively coupled one to the output ofbistable circuit 116 and one to its dual circuit 184. Thus, in the sameway as discussed for gate 119 the gate 187 is open whenever there is a 0pulse at the last stage 129 of the shift register 111 and closedwhenever there is a 1 pulse at the last stage 129 of the shift register111.

There may be intervals, during the transmission of the digital signalwhen no information is being transmitted, for example, if a speechwaveform is being transmitted these intervals occur between words.During these intervals the bistable circuits 120 to 129 all achieve a 0state and their dual circuits 130 to 139 all achieve a I state. Anunwanted adjustment of the variable filter 181 would then take place anda spurious low frequency noise signal would result. The gate 183mentioned above is arranged to close in these circumstances so that nosignal is passed to the filter 181. A respective input to an OR gate 196is coupled to the output of each AND gate associated with the firststage of the shift register 111, that is AND gates 140 and 150, (a lowfrequency signal filling the shift register with l signals and the dualregister with 0" signals will likewise produce an unwanted noisesignal). The output of the OR gate 196 is fed to the parallel input ofeach stage of a shift register 197 having the same number of stages asthe shift register 111. The serial input of the shift register 197 isfed with clock pulses from the clock 112 which feeds the shift register111. The serial output of the shift register 197 is fed via an inverter198 to the control gate 199 of the controlled gate 183. Thus when theshift register 111 fills with 0" or l pulses the OR gate produces a lpulse which is fed to the parallel input of each stage of the shiftregister 197. While the shift register remains filled with l or O pulsesthe OR gate remains open and the shift register 197 produces a series ofl pulses at its serial output, these are passed to the inverter 198which produces a 0" pulse output for every 1 pulse input. The controlledgate 183 is thus closed'and kept closed so that there is no input to thevariable filter, and therefore no output, as required. When the firstsignal" pulse (a O or a 1" depending on what the shift register 111 isfilled with) is received at the first stage of the shift register 111the OR gate 196 is closed. The next clock pulse produces a 0 pulse atthe first stage of the shift register 197. With successive clock pulsesthis 0" pulse is passed along the shift register 197 in unison with thefirst signal pulse in the shift register. When the 0" pulse reaches thelast stage of the shift register 197 the signal pulse will be at thelast stage 129 of the shift register 111 and the frequency response ofthe variable filter 181 will be set in accordance with the number oflike pulses following the first signal" pulse as described above. Withthe next clock pulse the 0 signal is passed out of the shift register197 to the inverter 198 which produces a 1" pulse to open the gate 183and thus let through the signal" pulse from the shift register 111.

The shift register 197 continues to produce output 0 pulses and so keepthe gate 183 open until the shift register again fills with like signalpulses l or 0) when the OR gate 196 will again produce a 1 pulse to setthe whole of the shift register to a l state and thus close the gate 183at least until the shift register 187 (and consequently the shiftregister 11]) completely passes through its contents at the time whenthe OR gate 196 was opened. This therefore provides a convenient limiton the lowest frequency which the decoder will produce since anyfrequency lower than that producing a number of pulses equal to thenumber of stages in the shift registers 111 and 197 will automaticallyproduce no output signal from the filter 181.

In this embodiment the variable filter is of the kind whose pass bandcan be varied by the variation of an analogue control signal, asdescribed above. In an alternative embodiment, described below, aplurality of filters, each having a different pass band, are providedand a digital control signal is used to select .the appropriate filter.A suitable circuit is illustrated in F IG.

Referring now to FIG. 3 a dual shift register 211 is connected toreceive clock pulses from a clock 212 and the data input signal to bedecoded. The parallel output of bistable circuits 220 to 229 and dualbistable circuits 230 to 239 of the dual shift register 211 areconnected to AND gates 240 to 249 and 250 to 259 the outputs of whichare coupled to respective shift registers 260 to 269 and 270 to 279 inan identical manner to the similar circuits of the embodiment of FIG. 2.A bistable circuit 216 having a dual bistable circuit 284 is connectedto the serial output of the shift register 211 to control AND gates 215and 288 which respectively provide appropriate clear" outputs to thebanks of bistable circuits 260 to 269 and 270 to 279 whenever the stateof bistable circuit 216 is different from that of bistable circuit 229as described in relation to the similar elements in the embodiment ofFIG. 2. The data signal passes from the output of bistable circuit 229to an adjusting circuit 282 where it is adjusted so that the l and the 0signals are equally spaced on either side of a datum level (normallyzero) and thence via a .gate 283 to a bank of gates 290 to 298 and,depending on which gate is open, to one of a bank of filters 300 to 308.y

The gate 283 is controlled by an OR gate 186 the inputs to which arecoupled to the outputs of the AND gates 240 and 250 associatedrespectively with the first stages 220 and 230 of the dual shiftregister 211; the output of the OR gate 186 is coupled via a shiftregister 187 and an inverter 188 to the control input of the gate 283 tocut off the output signal when the shift register fills up with likepulses during the intervals between units of information in the signal.

The appropriate filter for any series of pulses is selected as follows.Consider a train of four l" pulses arriving down the shift register whenthe first l pulse has just been transferred to bistable circuit 229. Thedual bistable circuit 239 will thus be in a state as will bistablecircuit 216 and the dual circuit to 216 will thus be in a l state. TheAND gate 288 produces a l signal to clear the bank of shift registers270 to 279 and because of the way the AND gates 250 to 259 are connectedthis bank of shift register (270 to 279) will remain cleared until theend of the train of l pulses the head of which has just reached bistablecircuit 229.

The inputs of AND gate 249 are both connected to the parallel output ofbistable circuit 229 so it will produce a 1 pulse and trigger AND gates248, 247 and 246 in succession, that is up to the last l pulse in thetrain. The chain is broken there and the remaining AND gates in thechain will remain closed. The outputs of the AND gates passes to a bankof parallel connected shift registers 260 to 269 and shift registers 266to 269 will switch to a 1" output state due to the l input produced bythe appropriate AND gates. A bank of exclusive OR gates 310 to 318 areconnected with each of two inputs coupled to the output of one of a pairof adjacent bistable circuits in the bank 260 to 269. Thus the exclusiveOR gate 310 has one input cou pled to the outputs of bistable circuit260 and one input coupled to the output of bistable 261 and exclusive ORgate 311 has an input from circuit 261 and an input from circuit 262 andsimilarly down the chain so that an output from the exclusive OR bank310 to 318 occurs in the present example from exclusive OR gate 315,which is coupled to the last bistable circuit of the chain in the lstate and the first bistable circuit in a 0" state.

The output from the exclusive OR gate 315 is passed to the control gateof the controlled gate 293 in the bank 290 to 298 via an OR gate 325 ina bank 320 to 328 to couple the serial output of the shift register 211to the filter circuit 303. A second input to each OR gate in the bank320 to 328 is coupled to the appropriate output of a bank of exclusiveOR circuits 330 to 338 coupled in the same way as the bank 310 to 318but to the dual side of the decoder to handle the 0" pulses of thesignal. Thus depending on the length of the pulses, an appropriatefilter circuit is selected from the bank 300 to 308 by opening a gatedetermined by the position of the last pulse in the train when the firstone reaches the end of the shift register 211 and is about to be passedto the filter bank. The bistable circuits will remain in the statedetermined at this instant until a clear signal is received along theclear line whereupon the dual side of the decoder will be set to handlethe next train of pulses which will be a train of 0 pulses. As mentionedearlier the switching time of the AND gates and bistable circuits isvery much shorter than the clock pulse intervals and so the gate to theappropriate filter circuit is opened substantially instantaneously withthe reception by circuit 129 of the first of a train of pulses.

What we claim is:

1. A method of digitally encoding an electrical input signalrepresenting a waveform such as a speech waveform, comprising the stepsof:

a. determining the time intervals between successive occurrences ofpredetermined amplitudes,

b. producing a first electrical output signal having pulses of differentlengths, each indicative of respective said time intervals,

c. quantizing said first electrical output signal to provide a digitalelectrical output signal, and

d. providing pulses of a predetermined length from selected quantizedpulse lengths of said digital electrical output signal to effect anon-linear quantization of said first electrical output signal.

2. The method of claim 1 wherein said predetermined amplitudes have aconstant value.

3. The method of claim 1 wherein said predetermined amplitudes vary independence on either or both the amplitude and frequency of saidelectrical input signal.

4. The method of claim 1 further comprising the step of: preferentiallyamplifying the components of the frequency spectrum of said input signalwhich characteristically have a low amplitude to ensure that saidcomponents achieve said predetermined amplitudes.

5. The method of claim 1 further including: the step of frequencyinversion of said electrical input signal prior to the step ofdetermining said time intervals between successive occurrences ofpredetermined amplitudes.

6. The method of claim 1, wherein said quantization is effected bypassing said first electrical output signal to one input of acoincidence circuit the other input of which is fed by a signal ofpredetermined substantially constant frequency.

7. The method of claim 6, wherein said predetermined substantiallyconstant frequency is at least twice the highest frequency of theelectrical input signal.

8. The method of claim 1, wherein said non-linear quantization iseffected in such a way as to produce a substantially equal number ofdifferent pulse lengths to represent each octave within the frequencyrange of the original signal waveform.

9. A circuit for encoding an electrical input signal representing awaveform such as a speech waveform, comprising: means for determiningthe time intervals between successive occurrences of predeterminedamplitudes and for providing a first electrical output signal havingpulses of different lengths each indicative of the length of respectivesaid time intervals; means for quantizing said pulse lengths of saidfirst electrical output signal to produce a digital electrical outputsignal; and means for providing quantized pulses of a predeterminedlength from selected quantized pulse lengths of said digital electricaloutput signal to effect a nonlinear quantization of said firstelectrical output signal.

10. The circuit of claim 9 wherein there are provided means forselectively amplifying components of the frequency spectrum of the inputsignal which characteristically have a low amplitude to ensure thatthese components achieve said predetermined amplitudes.

11. The circuit of claim 9, wherein said means for providing said firstelectrical output signal having pulses of different lengths comprises aninfinite clipping circuit.

12. The circuit of claim 9, wherein said means for providingpredetermined quantized pulse lengths from selected quantized pulselengths to effect a non-linear quantization of said first electricaloutput signal comprise: a first shift register having a serial input,and a plurality of parallel outputs, one for each stage of said registerand a second shift register having a serial input, a serial output, anda plurality of parallel inputs, one for each stage of said register, theparallel outputs of said first shift register being interconnected withthe parallel inputs of said second shift register such that the stagesof said first shift register positioned to receive a selected pulselength are coupled to the stages of said second shift rwgisterpositioned to hold said predetermined pulse lengths which are to beprovided in place of said selected pulse lengths.

13. The circuit of claim 12, wherein said digital electrical outputsignal has only two discrete amplitudes and said first shift register isa dual register each side of which handles signals representing arespective amplitude of said electrical output signal.

14. The circuit of claim 13, wherein said dual register also has aplurality of parallel outputs, one for each stage of said dual register;a third shift register having a serial input, a serial output, and aplurality of parallel inputs, one for each stage of said register; saidparallel outputs of said dual register being interconnected with saidparallel inputs of said third shift register such that the stages ofsaid dual register positioned to receive selected pulse lengths arecoupled to stages of said third shift register positioned to hold saidpredetermined pulse lengths which are to be provided in place of saidselected pulse lengths.

15. The circuit of claim 14, wherein said second and said third shiftregisters also have a plurality .of parallel outputs, one from eachstage of said register, said parallel outputs being fed to a presetinput of each corresponding stage in said first and said dual registerto ensure that corresponding stages are always in the same state whensaid second and third registers are in use.

16. A circuit for decoding a quantized digital signal of the typeencoded in dependence on the time intervals between successiveoccurrences of predetermined amplitudes in the original informationsignal comprismg:

a. a variable output circuit,

b. means for determining the length of each successive pulse of saiddigital signal,

c. means for delaying said digital signal,

d. means for adjusting said variable output circuit in dependence onsaid pulse length while said delay means is delaying said pulse lengthof said signal, and

e. means for passing said digital signal to said adjusted output circuitto provide an output waveform related to said quantized digital signal.

17. The circuit of claim 16, wherein said variable output circuit is alow pass filter circuit the frequency response of which is adjustablesuch that the cutoff frequency is decreased to a relatively low valuefor a long pulse, and increased to a relatively high value for a shortpulse.

18. The circuit of claim 17, wherein said means for determining thelength of successive pulses comprises:

dalh'f 't h' al't f all t- 3mg, or ie o r a c sta i g t a f s i d re gstgn si con a nd thirdshift registers having a plurality of parallelinputs, one for each stage of each said register; said parallel outputsof said dual register being interconnected with said parallel inputs ofsaid second and third. shift registers whereby a train of like pulseswhich is about to pass out of said dual register will switch acorrespond ing number of stages of said second or said third register toprovide an indication of the pulse length of the signal about to pass tosaid variable filter circuit.

19. The circuit of claim 18, wherein said means for determining thelength of successive pulses further includes: said second and thirdshift registers having a plurality of parallel outputs, one for eachstage of said registers; two analogue adding circuits, the inputs ofrespective said analogue adding circuits being coupled to respectivesaid parallel outputs of said second and third shift registers; theoutputs of said analogue adding circuits being coupled to a controlinput of said variable filter circuit.

20. The circuit of claim 17, wherein said variable filter circuitcomprises a plurality of fixed filter circuits each having a differentfrequency response, and a cooperating switching circuit for selectingthe appropriate filter in dependence on the length of the pulse to bedecoded.

21. The circuit of claim 20, wherein said means for determining thelength of successive pulse comprises: a dual shift register having aserial input, a serial output to the variable filter circuit, and aplurality of parallel outputs, one for each stage of the register;second and third shift registers each having a plurality of parallelinputs and a plurality of parallel outputs, one of each for each stageof each of said registers; means interconnecting said parallel outputsof respective sides of said dual register with said parallel inputs ofsaid second and third registers respectively, whereby a train of likepulses which is about to pass out of said dual register will switch acorresponding number of stages of whichever of said second or thirdregisters is connected to that side of said dual register; and aplurality of exclusive OR gates coupled to said parallel outputs of saidsecond and third registers whereby the end of said train of like pulsesis detected and a signal passed to the appropriate part of saidswitching circuit.

22. A method of decoding a digital signal of the type encoded independence on the time intervals between successive occurrences, in theoriginal information signal, of predetermined amplitudes, comprising thesteps of:

a. determining the length of each successive pulse of the digitalsignal,

b. delaying the digital signal while adjusting the frequency response ofa variable output circuit in dependence on the pulse lengths, and

c. then passing said signal through said, now adjusted, output circuitto provide an output waveform corresponding to said digital signal.

1. A method of digitally encoding an electrical input signalrepresenting a waveform such as a speech waveform, comprising the stepsof: a. determining the time intervals between successive occurrences ofpredetermined amplitudes, b. producing a first electrical output signalhaving pulses of different lengths, each indicative of respective saidtime intervals, c. quantizing said first electrical output signal toprovide a digital electrical output signal, and d. providing pulses of apredetermined length from selected quantized pulse lengths of saiddigital electrical output signal to effect a non-linear quantization ofsaid first electrical output signal.
 2. The method of claim 1 whereinsaid predetermined amplitudes have a constant value.
 3. The method ofclaim 1 wherein said predetermined amplitudes vary in dependence oneither or both the amplitude and frequency of said electrical inputsignal.
 4. The method of claim 1 further comprising the step of:preferentially amplifying the components of the frequency spectrum ofsaid input signal which characteristically have a low amplitude toensure that said components achieve said predetermined amplitudes. 5.The method of claim 1 further including: the step of frequency inversionof said electrical input signal prior to the step of determining saidtime intervals between successive occurrences of predeterminedamplitudes.
 6. The method of claim 1, wherein said quantization iseffected by passing said first electrical output signal to one input ofa coincidence circuit the other input of which is fed by a signal ofpredetermined substantially constant frequency.
 7. The method of claim6, wherein said predetermined substantially constant frequency is atleast twice the highest frequency of the electrical input signal.
 8. Themethod of claim 1, wherein said non-linear quantization is effected insuch a way as to produce a substantially equal number of different pulselengths to represent each octave within the frequency range of theoriginal signal waveform.
 9. A circuit for encoding an electrical inputsignal representing a waveform such as a speech waveform, comprising:means for determining the time intervals between successive occurrencesof predetermined amplitudes and for providing a first electrical outputsignal having pulses of different lengths each indicative of the lengthof respective said time intervals; means for quantizing said pulselengths of said first electrical output signal to produce a digitalelectrical output signal; and means for prOviding quantized pulses of apredetermined length from selected quantized pulse lengths of saiddigital electrical output signal to effect a non-linear quantization ofsaid first electrical output signal.
 10. The circuit of claim 9 whereinthere are provided means for selectively amplifying components of thefrequency spectrum of the input signal which characteristically have alow amplitude to ensure that these components achieve said predeterminedamplitudes.
 11. The circuit of claim 9, wherein said means for providingsaid first electrical output signal having pulses of different lengthscomprises an infinite clipping circuit.
 12. The circuit of claim 9,wherein said means for providing predetermined quantized pulse lengthsfrom selected quantized pulse lengths to effect a non-linearquantization of said first electrical output signal comprise: a firstshift register having a serial input, and a plurality of paralleloutputs, one for each stage of said register and a second shift registerhaving a serial input, a serial output, and a plurality of parallelinputs, one for each stage of said register, the parallel outputs ofsaid first shift register being interconnected with the parallel inputsof said second shift register such that the stages of said first shiftregister positioned to receive a selected pulse length are coupled tothe stages of said second shift rwgister positioned to hold saidpredetermined pulse lengths which are to be provided in place of saidselected pulse lengths.
 13. The circuit of claim 12, wherein saiddigital electrical output signal has only two discrete amplitudes andsaid first shift register is a dual register each side of which handlessignals representing a respective amplitude of said electrical outputsignal.
 14. The circuit of claim 13, wherein said dual register also hasa plurality of parallel outputs, one for each stage of said dualregister; a third shift register having a serial input, a serial output,and a plurality of parallel inputs, one for each stage of said register;said parallel outputs of said dual register being interconnected withsaid parallel inputs of said third shift register such that the stagesof said dual register positioned to receive selected pulse lengths arecoupled to stages of said third shift register positioned to hold saidpredetermined pulse lengths which are to be provided in place of saidselected pulse lengths.
 15. The circuit of claim 14, wherein said secondand said third shift registers also have a plurality of paralleloutputs, one from each stage of said register, said parallel outputsbeing fed to a preset input of each corresponding stage in said firstand said dual register to ensure that corresponding stages are always inthe same state when said second and third registers are in use.
 16. Acircuit for decoding a quantized digital signal of the type encoded independence on the time intervals between successive occurrences ofpredetermined amplitudes in the original information signal comprising:a. a variable output circuit, b. means for determining the length ofeach successive pulse of said digital signal, c. means for delaying saiddigital signal, d. means for adjusting said variable output circuit independence on said pulse length while said delay means is delaying saidpulse length of said signal, and e. means for passing said digitalsignal to said adjusted output circuit to provide an output waveformrelated to said quantized digital signal.
 17. The circuit of claim 16,wherein said variable output circuit is a low pass filter circuit thefrequency response of which is adjustable such that the cutoff frequencyis decreased to a relatively low value for a long pulse, and increasedto a relatively high value for a short pulse.
 18. The circuit of claim17, wherein said means for determining the length of successive pulsescomprises: a dual shift register having a plurality of parallel outputs,one for each stage of said register; second aNd third shift registershaving a plurality of parallel inputs, one for each stage of each saidregister; said parallel outputs of said dual register beinginterconnected with said parallel inputs of said second and third shiftregisters whereby a train of like pulses which is about to pass out ofsaid dual register will switch a corresponding number of stages of saidsecond or said third register to provide an indication of the pulselength of the signal about to pass to said variable filter circuit. 19.The circuit of claim 18, wherein said means for determining the lengthof successive pulses further includes: said second and third shiftregisters having a plurality of parallel outputs, one for each stage ofsaid registers; two analogue adding circuits, the inputs of respectivesaid analogue adding circuits being coupled to respective said paralleloutputs of said second and third shift registers; the outputs of saidanalogue adding circuits being coupled to a control input of saidvariable filter circuit.
 20. The circuit of claim 17, wherein saidvariable filter circuit comprises a plurality of fixed filter circuitseach having a different frequency response, and a cooperating switchingcircuit for selecting the appropriate filter in dependence on the lengthof the pulse to be decoded.
 21. The circuit of claim 20, wherein saidmeans for determining the length of successive pulse comprises: a dualshift register having a serial input, a serial output to the variablefilter circuit, and a plurality of parallel outputs, one for each stageof the register; second and third shift registers each having aplurality of parallel inputs and a plurality of parallel outputs, one ofeach for each stage of each of said registers; means interconnectingsaid parallel outputs of respective sides of said dual register withsaid parallel inputs of said second and third registers respectively,whereby a train of like pulses which is about to pass out of said dualregister will switch a corresponding number of stages of whichever ofsaid second or third registers is connected to that side of said dualregister; and a plurality of exclusive OR gates coupled to said paralleloutputs of said second and third registers whereby the end of said trainof like pulses is detected and a signal passed to the appropriate partof said switching circuit.
 22. A method of decoding a digital signal ofthe type encoded in dependence on the time intervals between successiveoccurrences, in the original information signal, of predeterminedamplitudes, comprising the steps of: a. determining the length of eachsuccessive pulse of the digital signal, b. delaying the digital signalwhile adjusting the frequency response of a variable output circuit independence on the pulse lengths, and c. then passing said signal throughsaid, now adjusted, output circuit to provide an output waveformcorresponding to said digital signal.